| SNo | Project Title | Domain | Year |
|---|---|---|---|
| VLSI2023 | Implementation of a Multipath Fully Differential OTA in 0.18-μm CMOS Process | LOW POWER | VLSI-2023 |
| VLSI2023 | VLSI Design of a High-Performance Multicontext MQ Arithmetic Coder | LOW POWER | VLSI-2023 |
| VLSI2023 | A Lightweight True Random Number Generator for Root of Trust Applications | LOW POWER | VLSI-2023 |
| VLSI2023 | A Process-Adaptive Cell-Based Cyclic Time-to-Digital Converter Using One-Way Varactor Cells | LOW POWER | VLSI-2023 |
| VLSI2023 | An Improved MOS Self-Biased Ring Amplifier and Modified Auto-Zeroing Scheme | LOW POWER | VLSI-2023 |
| VLSI2023 | A Framework for Reliability Analysis of Combinational Circuits Using Approximate Bayesian Inference | LOW POWER | VLSI-2023 |
| VLSI2023 | COPMA: Compact and Optimized Polynomial Multiplier Accelerator for High-Performance Implementation of LWR-Based PQC | LOW POWER | VLSI-2023 |
| VLSI2023 | Energy-Efficient Wide-Range Level Shifter With a Logic Error Detection Circuit | LOW POWER | VLSI-2023 |
| VLSI2023 | MInSC: A VLSI Architecture for Myocardial Infarction Stages Classifier for Wearable Healthcare Applications | LOW POWER | VLSI-2023 |
| VLSI2023 | Low-Power Redundant-Transition-Free TSPC Dual-Edge-Triggering Flip-Flop Using Single-Transistor-Clocked Buffer | LOW POWER | VLSI-2023 |
| VLSI2023 | A Reliable and High-Speed 6T Compute-SRAM Design With Dual-Split-VDD Assist and Bitline Leakage Compensation | LOW POWER | VLSI-2023 |
| VLSI2023 | A High-Performance Dual-Context MQ Encoder Architecture Based on Extended Lookup Table | LOW POWER | VLSI-2023 |
| VLSI2023 | Single Exact Single Approximate Adders and Single Exact Dual Approximate Adders | LOW POWER | VLSI-2023 |
| VLSI2023 | A Triple Burst Error Correction Based on Region Selection Code | LOW POWER | VLSI-2023 |
| VLSI2023 | A 28 nm 16 Kb Bit-Scalable Charge-Domain Transpose 6T SRAM In-Memory Computing Macro | LOW POWER | VLSI-2023 |
| VLSI2023 | Toward the Multiple Constant Multiplication at Minimal Hardware Cost | LOW POWER | VLSI-2023 |
| VLSI2023 | BP-SCIM: A Reconfigurable 8T SRAM Macro for Bit-Parallel Searching and Computing In-Memory | LOW POWER | VLSI-2023 |
| VLSI2023 | Energy-Efficient Single-Ended Read/Write 10T Near-Threshold SRAM | LOW POWER | VLSI-2023 |
| VLSI2023 | A Rail-to-Rail Transconductance Amplifier Based on Current Generator Circuits | LOW POWER | VLSI-2023 |
| VLSI2023 | A Low-Power PPG Processor for Real-Time Biometric Identification and Heart Rate Estimation | LOW POWER | VLSI-2023 |
| VLSI2023 | AxPPA: Approximate Parallel Prefix Adders | AREA EFFICIENT/ TIMING & DELAY REDUCTION | VLSI-2023 |
| VLSI2023 | Reliability Evaluation and Fault Tolerance Design for FPGA Implemented Reed Solomon (RS) Erasure Decoders | AREA EFFICIENT/ TIMING & DELAY REDUCTION | VLSI-2023 |
| VLSI2023 | Architectural Comparison Model for Area-Efficient PMAP Turbo-Decoders | AREA EFFICIENT/ TIMING & DELAY REDUCTION | VLSI-2023 |
| VLSI2023 | A High-Speed FPGA-Based True Random Number Generator Using Metastability With Clock Managers | AREA EFFICIENT/ TIMING & DELAY REDUCTION | VLSI-2023 |
| VLSI2023 | Real-Time FPGA Investigation of Potential FEC Schemes for 800G-ZR/ZR+ Forward Error Correction | AREA EFFICIENT/ TIMING & DELAY REDUCTION | VLSI-2023 |
| VLSI2023 | Design of a High Throughput Pseudorandom Number Generator Based on Discrete Hyper-Chaotic System | AREA EFFICIENT/ TIMING & DELAY REDUCTION | VLSI-2023 |
| VLSI2023 | An Iterative Montgomery Modular Multiplication Algorithm With Low Area-Time Product | AREA EFFICIENT/ TIMING & DELAY REDUCTION | VLSI-2023 |
| VLSI2023 | Multiple-Mode-Supporting Floating-Point FMA Unit for Deep Learning Processors | AREA EFFICIENT/ TIMING & DELAY REDUCTION | VLSI-2023 |
| VLSI2023 | Streaming Dilated Convolution Engine | AREA EFFICIENT/ TIMING & DELAY REDUCTION | VLSI-2023 |
| VLSI2023 | Area-Efficient Parallel Multiplication Units for CNN Accelerators With Output Channel Parallelization | AREA EFFICIENT/ TIMING & DELAY REDUCTION | VLSI-2023 |
| VLSI2023 | Two Efficient Approximate Unsigned Multipliers by Developing New Configuration for Approximate 4:2 Compressors | AREA EFFICIENT/ TIMING & DELAY REDUCTION | VLSI-2023 |
| VLSI2023 | Optimizing Ternary Multiplier Design With Fast Ternary Adder | AREA EFFICIENT/ TIMING & DELAY REDUCTION | VLSI-2023 |
| VLSI2023 | Highly Accurate and Energy Efficient Binary-Stochastic Multipliers for Fault-Tolerant Applications | AREA EFFICIENT/ TIMING & DELAY REDUCTION | VLSI-2023 |
| VLSI2023 | An Ultra-Efficient Approximate Multiplier With Error Compensation for Error-Resilient Applications | AREA EFFICIENT/ TIMING & DELAY REDUCTION | VLSI-2023 |
| VLSI2023 | Simplified Compressor and Encoder Designs for Low-Cost Approximate Radix-4 Booth Multiplier | AREA EFFICIENT/ TIMING & DELAY REDUCTION | VLSI-2023 |
| VLSI2023 | Performance Screening Using Functional Path Ring Oscillators | AREA EFFICIENT/ TIMING & DELAY REDUCTION | VLSI-2023 |
| VLSI2023 | A Methodology for the Design of Fault Tolerant Parallel Digital Channelizers on SRAM-FPGAs | AREA EFFICIENT/ TIMING & DELAY REDUCTION | VLSI-2023 |
| VLSI2023 | Area Efficient Approximate 4–2 Compressor and Probability-Based Error Adjustment for Approximate Multiplier | AREA EFFICIENT/ TIMING & DELAY REDUCTION | VLSI-2023 |
| VLSI2023 | Booth Encoding-Based Energy Efficient Multipliers for Deep Learning Systems | AREA EFFICIENT/ TIMING & DELAY REDUCTION | VLSI-2023 |
| VLSI2023 | Low-Complexity Distributed Arithmetic-Based Architecture for Inner-Product of Variable Vectors | AREA EFFICIENT/ TIMING & DELAY REDUCTION | VLSI-2023 |
| VLSI2023 | Area-Efficient Intellectual Property (IP) Design of Advanced Encryption Standard | AREA EFFICIENT/ TIMING & DELAY REDUCTION | VLSI-2023 |
| VLSI2023 | Synthesis of Approximate Parallel-Prefix Adders | AREA EFFICIENT/ TIMING & DELAY REDUCTION | VLSI-2023 |
| VLSI2023 | ReAdapt: A Reconfigurable Datapath for Runtime Energy-Quality Scalable Adaptive Filters | HIGH SPEED DATA TRANSMISSION | VLSI-2023 |
| VLSI2023 | Algorithm and Architecture Design of Random Fourier Features-Based Kernel Adaptive Filters | HIGH SPEED DATA TRANSMISSION | VLSI-2023 |
| VLSI2023 | A High-Precision Folding Time-to-Digital Converter Implemented in Kintex-7 FPGA | HIGH SPEED DATA TRANSMISSION | VLSI-2023 |
| VLSI2023 | FPGA Implementation of IIR Notch and Anti-Notch Filters with an Application to Localization of Protein Hot-Spots | HIGH SPEED DATA TRANSMISSION | VLSI-2023 |
| VLSI2023 | A 1.6-mW Sparse Deep Learning Accelerator for Speech Separation | HIGH SPEED DATA TRANSMISSION | VLSI-2023 |
| VLSI2023 | Low-Complexity Precision-Scalable Multiply-Accumulate Unit Architectures for Deep Neural Network Accelerators | HIGH SPEED DATA TRANSMISSION | VLSI-2023 |
| VLSI2023 | Interpolated Individual Weighting Subband Volterra Filter for Nonlinear Active Noise Control | HIGH SPEED DATA TRANSMISSION | VLSI-2023 |
| VLSI2023 | The Auto-Correlation Function Aided Sparse Support Matrix Machine for EEG-Based Fatigue Detection | HIGH SPEED DATA TRANSMISSION | VLSI-2023 |
| VLSI2023 | Time-Domain Multiply-Accumulator using Digital-to-Time Multiplier for CNN Processors in 28-nm CMOS | HIGH SPEED DATA TRANSMISSION | VLSI-2023 |
| VLSI2023 | Hybrid Protection of Digital FIR Filters | HIGH SPEED DATA TRANSMISSION | VLSI-2023 |
| VLSI2023 | Scalable Resource Optimized LUT-Based All-Digital Transmitter | HIGH SPEED DATA TRANSMISSION | VLSI-2023 |
| VLSI2023 | A High-Throughput and Flexible Architecture Based on a Reconfigurable Mixed-Radix FFT With Twiddle Factor Compression and Conflict-Free Access | HIGH SPEED DATA TRANSMISSION | VLSI-2023 |
| VLSI2023 | Serial Butterflies for Non-Power-of-Two FFT Architectures in 5G and Beyond | HIGH SPEED DATA TRANSMISSION | VLSI-2023 |
| VLSI2023 | An Efficient Multi-Secret Image Sharing System Based on Chinese Remainder Theorem and Its FPGA Realization | VLSI Design of Image, Video and Audio Processing | VLSI-2023 |
| VLSI2023 | An FPGA-Based Transformer Accelerator Using Output Block Stationary Dataflow for Object Recognition Applications | VLSI Design of Image, Video and Audio Processing | VLSI-2023 |
| VLSI2023 | VLSI Design of Saturation-Based Image Dehazing Algorithm | VLSI Design of Image, Video and Audio Processing | VLSI-2023 |
| VLSI2023 | An Efficient Image Encryption Algorithm Based on Innovative DES Structure and Hyperchaotic Keys | VLSI Design of Image, Video and Audio Processing | VLSI-2023 |
| VLSI2023 | Nontraditional Design of Dynamic Logics Using FDSOI for Ultra-Efficient Computing | VLSI | VLSI-2023 |
| VLSI2023 | Self-Adaptive Gate Control for Efficient Escape from Local Minimum Energy on Invertible Logic | VLSI | VLSI-2023 |
| VLSI2023 | Quaternary Reversible Circuit Optimization for Scalable Multiplexer and Demultiplexer | VLSI | VLSI-2023 |
| VLSI2023 | A Flexible-Channel MDF Architecture for Pipelined Radix-2 FFT | VLSI | VLSI-2023 |
| VLSI2023 | Wide word-length carry-select adder design using ripple carry and carry look-ahead method based hybrid 4-bit carry generator | VLSI | VLSI-2023 |
| VLSI2023 | FlexKA: A Flexible Karatsuba Multiplier Hardware Architecture for Variable-Sized Large Integers | VLSI | VLSI-2023 |
| VLSI2023 | Hardware Implementation of High-Throughput S-Box in AES for Information Security | VLSI | VLSI-2023 |
| VLSI2023 | Hybrid Protection of Digital FIR Filters | VLSI | VLSI-2023 |
| VLSI2023 | Low power resource efficient CORDIC enabled neuron architecture using 45 nm CMOS technology | VLSI | VLSI-2023 |
| VLSI2023 | Numerical model for 32-bit magnonic ripple carry adder | VLSI | VLSI-2023 |
| VLSI2023 | Optimized reverse converters with multibit soft error correction support at 7nm technology | VLSI | VLSI-2023 |
| VLSI2023 | Power and area efficient FIR filter architecture in digital encephalography systems | VLSI | VLSI-2023 |
| VLSI2023 | Reconfigurable Hyper-Parallel Fast Fourier Transform Processor Based on Bit-Serial Computing | VLSI | VLSI-2023 |
| VLSI2023 | Serial Butterflies for Non-Power-of-Two FFT Architectures in 5G and Beyond | VLSI | VLSI-2023 |
| High Speed 2023 VLSI Design projects ( CDMA, RTOS, DSP, RF, IF, etc) | |||
| Low Power 2023 VLSI Design projects | |||
| Area Efficient 2023 VLSI Design projects | |||
| Audio processing 2023 VLSI Design projects | |||
| Signal Processing 2023 VLSI Design projects | |||
| Image Processing 2023 VLSI Design projects | |||
| Backend 2023 VLSI Design projects ( CMOS, TFET, BisFET, FeFET, etc) | |||
| Timing & Delay Reduction 2023 VLSI Projects | |||
| Internet of Things 2023 VLSI Projects | |||
| Testing, Reliability and Fault Tolerance 2023 VLSI Projects | |||
| 2023 VLSI Applications ( Communicational, Video, Security, Sensor Networks, etc) | |||
| SOC 2023 VLSI Projects | |||
| Network on Chip 2023 VLSI Projects | |||
| Wireless Communication 2023 VLSI Projects | |||
| 2023 VLSI Verifications Projects ( UVM, OVM, VVM, System Verilog | |||
| 2023 VLSI IEEE Projects in VHDL | |||
| 2023 VLSI IEEE Projects in Verilog HDL | |||
| 2023 VLSI IEEE Projects in HSPICE | |||
| 2023 VLSI IEEE Projects in Tanner EDA | |||
| 2023 VLSI IEEE Projects in DSCH3 | |||
| 2023 VLSI IEEE Projects in Microwind |
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